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CS5529
26
DS246F5
PIN DESCRIPTIONS
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 10, 11.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock (powered
relative to VD+) can be supplied into the XIN pin to provide the master clock for the device.
Control Pins and Serial Data I/O
CS - Chip Select, Pin 8.
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
SDI - Serial Data Input, Pin 15.
SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.
SDO - Serial Data Output, Pin 14.
SDO is the serial data output. It will output a high impedance state if CS = 1.
SCLK - Serial Clock Input, Pin 9.
A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins
respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin
will recognize clocks only when CS is low.
1
2
3
4
5
6
7
813
14
15
16
17
18
19
20
VREF+
VREF-
D3
D2
D1
SDI
SDO
VD+
CS
D0
A1
A0
AIN-
AIN+
VA+
VA-
9
10
11
12
DGND
XIN
XOUT
SCLK
VOLTAGE REFERENCE INPUT
LOGIC OUTPUT (DIGITAL)
SERIAL DATA INPUT
SERIAL DATA OUTPUT
POSITIVE DIGITAL POWER
DIGITAL GROUND
CRYSTAL IN
CHIP SELECT
LOGIC OUTPUT (DIGITAL)
LOGIC OUTPUT (ANALOG)
DIFFERENTIAL ANALOG INPUT
POSITIVE ANALOG POWER
NEGATIVE ANALOG POWER
CRYSTAL OUT
SERIAL CLOCK INPUT
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